The invention relates to a memory cell configuration with memory elements having a layer structure with a giant magnetoresistive effect.
Layer structures with a magnetoresistive effect are known from the reference titled xe2x80x9cTechnology Analysis XMR-Technologien, Technologiefrxc3xcherkennung [XMR Technologies, Technology Detection at an Early Stage]xe2x80x9d, author Stefan Mengel, published by VDI-Technologiezentrum Physikalische Technologien. Depending on the construction of the layer structure, a distinction is made between a giant magnetoresistance (GMR) element, a tunneling magnetoresistance (TMR) element, an anisotropic magnetoresistance (AMR) element and a colossal magnetoresistance (CMR) element.
The term GMR element is used by experts for layer structures which have at least two ferromagnetic layers and a non-magnetic, conductive layer disposed in between and exhibit the so-called giant magnetoresistance effect, that is to say a large magnetoresistive effect in comparison with the AMR (anisotropic magnetoresistance) effect. The GMR effect encompasses the fact that the electrical resistance of the GMR element is dependent on whether the magnetizations in the two ferromagnetic layers are oriented in a parallel or an anti-parallel manner.
The term TMR element is used by experts for xe2x80x9ctunneling magnetoresistancexe2x80x9d layer structures which have at least two ferromagnetic layers and an insulating, non-magnetic layer disposed in between. In this case, the insulating layer is so thin that a tunneling current occurs between the two ferromagnetic layers. These layer structures likewise exhibit a magnetoresistive effect that is caused by a spin-polarized tunneling current through the insulating, non-magnetic layer disposed between the two ferromagnetic layers. In this case, too, the electrical resistance of the TMR element is dependent on whether the magnetizations in the two ferromagnetic layers are oriented in a parallel or antiparallel manner.
The AMR effect is manifested in the fact that the resistance in magnetized conductors is different parallel and perpendicular to the magnetization direction. It is a volume effect and thus occurs in single ferromagnetic layers.
A further magnetoresistance effect, which is called colossal magnetoresistance effect because of its magnitude (xcex94R/R=100 percent . . . 400 percent at room temperature), requires a high magnetic field for changing over between the magnetization states on account of its high coercive forces.
It has been proposed (see, for example the reference by D. D. Tang et al, IEDM 95, pages 997 to 999, D. D. Tang et al, IEEE Trans. on Magnetics, Vol. 31, No. 6, 1995, pages 3206 to 3208, F. W. Patten et al, Int. Non Volatile Memory Technology Conf., 1996, pages 1 to 2) to use GMR elements as memory elements in a memory cell configuration. For this purpose, GMR elements in which the magnetization direction of one ferromagnetic layer is fixed for example by an adjacent antiferromagnetic layer are used as memory elements. The memory elements are connected in series via read lines. Word lines run transversely with respect to the latter and are insulated both from the read lines and from the memory elements. Signals applied to the word lines cause a magnetic field as a result of the current flowing in the word line, which magnetic field, given a sufficient strength, influences the memory elements situated underneath. In order to write information, signals are applied to a bit line and a word line, which are designated as X/Y lines and cross one another above the memory cell to be written to, which signals cause, at the crossover point, a magnetic field which is sufficient for the magnetization reversal. In order to read the information, a signal is applied to the word line, which signal switches the relevant memory cell back and forth between the two magnetization states. The current through the read line is measured and the resistance of the corresponding memory element is determined from the current.
The reference by S. Tehrani et al., IEDM 96, page 193 et seq., proposes using a GMR element having ferromagnetic layers of different thicknesses as the memory element. The magnetic field for writing information is dimensioned such that it only influences the magnetization in the thinner of the two ferromagnetic layers. The magnetization in the thicker of the two ferromagnetic layers remains uninfluenced by it.
It is accordingly an object of the invention to provide a memory cell configuration that overcomes the above-mentioned disadvantages of the prior art devices of this general type, which has memory elements with a magnetoresistive effect that can be fabricated with an increased packing density.
With the foregoing and other objects in view there is provided, in accordance with the invention, a memory cell configuration, including:
a plurality of word lines running substantially parallel to one another;
a plurality of bit lines running substantially parallel to one another and running transversely with respect to the word lines; and
memory elements each having a layer structure with a magnetoresistive effect and disposed between one of the word lines and one of the bit lines, and the memory elements disposed in at least two layers disposed one above another.
The memory cell configuration has the word lines running essentially parallel to one another and the bit lines running essentially parallel to one another, with the word lines running transversely with respect to the bit lines. Memory elements having a layer structure with a magnetoresistive effect are provided, which memory elements are respectively disposed between one of the word lines and one of the bit lines.
In the literature, the term X-line or Y-line is also often used for the word and bit lines in connection with magnetic memories.
The memory elements are disposed in at least two layers. The layers are stacked one above the other. As a result, the area required by each memory element decreases and the packing density is increased. The larger the number of layers that are stacked one above the other, the-higher the packing density that can be attained. In this case, each layer of memory elements is disposed between two line planes, one line plane containing bit lines and the other line plane containing word lines. The bit lines and the word lines cross one another. A line plane that contains bit lines or word lines is respectively provided between adjacent layers.
The word lines and the bit lines, which cross one another, can each be fabricated with minimum dimensions and spacings of a minimum feature size F, resulting in an area requirement per memory element of 4F2 per layer. Overall, an area requirement of 4F2/n per memory element results in the memory cell configuration given n layers.
The memory cell configuration is preferably realized using thin-film technology on a semiconductor substrate. Components for addressing the memory cell configuration are contained in the semiconductor substrate.
All known TMR elements and GMR elements in a current perpendicular to plane (CPP) configuration are suitable as the memory element. The GMR effect is greater if the current flows perpendicularly through the layer stack (CPP) than if the current flows in parallel in the layers (CIP current in plane). Furthermore, all XMR elements are suitable, the elements having two magnetization states with a different resistance, it being possible to switch back and forth between the states by the application of a magnetic field whose magnitude is acceptable for the memory application.
Preferably, the memory elements each have two ferromagnetic layers and a non-magnetic, insulating (TMR) or conductive (GMR) layer disposed in between. The memory elements each have two magnetization states. It is advantageous to use an insulating, non-magnetic layer (TMR element) because higher element resistances (xe2x89xa7100 kxcexa9) can thereby be obtained, which are more favorable with regard to power consumption and signal/noise ratio.
One of the ferromagnetic layers is preferably disposed such that it is adjacent to an antiferromagnetic layer, which fixes the magnetization direction in the adjacent ferromagnetic layer. Materials containing at least one of the elements Fe, Mn, Ni, Ir, Tb and O are suitable, inter alia, for the antiferromagnetic layer.
As an alternative, the memory elements may each have two ferromagnetic layers and a non-magnetic layer disposed in between, one of the ferromagnetic layers being thicker than the other ferromagnetic layer or the ferromagnetic layers being formed from different materials with different magnetic properties, or have a non-magnetic, non-insulating layer. The effect achieved as a result of this is that only one ferromagnetic layer is subjected to magnetization reversal, while the other remains uninfluenced.
Materials containing at least one of the elements Fe, Ni, Co, Cr, Mn, Gd and Dy are suitable, inter alia, for the ferromagnetic layers. The thickness of the ferromagnetic layers is at most 20 nm and preferably lies in the range between 2 and 10 nm. Al2O3, NiO, HfO2, TiO2, NbO or SiO2 is suitable as an insulating material for the non-magnetic layer, which acts as a tunneling insulator. Cu or Ag is suitable as a non-insulating material for the non-magnetic layer. The thickness of the non-magnetic layer lies in the range of between 1 and 4 nm, preferably between 2 and 3 nm.
The memory elements preferably have dimensions in the range of between 0.05 xcexcm and 20 xcexcm. They may be configured such that they are square or elongate, inter alia.
In order to write information to one of the memory elements, a respective signal is applied to the associated word line and to the associated bit line. As a result, a current flows via the word line and the bit line and induces a magnetic field in each case. At the crossover point of the word line and the bit line, the total magnetic field resulting from superposition of the two magnetic fields is large enough to ensure magnetization reversal of the memory element situated there. Outside the crossover point, the individual magnetic fields are too small for magnetization reversal of the memory elements situated there.
The information can be read in different ways. In order to read the information, a signal can be applied to the word line, which signal switches the relevant memory element back and forth from a first magnetization state to a second magnetization state. A current through the bit line connected to the memory element is then measured. If the magnetization state is switched over during this operation, then the current changes. A conclusion about the stored information is drawn from the occurrence or non-occurrence of a current change. If the magnetization state is altered during the read-out operation, then the original information must subsequently be written back.
Preferably, the bit lines are each connected to a sense amplifier by which a potential on the respective bit line can be regulated to a reference potential and at which an output signal can be picked off. The memory elements are respectively connected between the associated word line and bit line. In order to read the memory cell configuration, all the word lines that are not selected are put at the reference potential. A signal with a different potential is applied to the selected word line. A current path from the selected word line to all the bit lines is closed as a result of this. The resistance of the memory element situated at the crossover point between the word line and the respective bit line can be determined from the output signal at the respective sense amplifier, the electrical characteristic parameters of the sense amplifier, such as the feedback resistance, for example, and the reference potential and the bit line resistance. An alteration of the stored information does not occur, therefore, during the reading of the memory cell configuration.
The sense amplifier preferably has a feedback operational amplifier. The non-inverting input of the operational amplifier is connected to a reference potential, for example to ground. The bit line is connected to the inverting input. If the reference potential is 0 volts, then the operational amplifier ensures that 0 volts are present on the bit line. The output signal of the operational amplifier is a measure of the resistance of the selected memory element.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a memory cell configuration, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.